1. Field of the Invention
The present invention relates to an insulated gate bipolar transistor (hereinafter referred to as IGBT), and more particularly, it relates to prevention of a latch-up phenomenon of a parasitic thyristor.
2. Description of the Prior Art
In general, an IGBT device is formed by a number of parallel-connected IGBT elements (hereinafter referred to as IGBT cells), as shown in FIG. 1 of IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-31, No. 6, JUNE 1984, PP. 821-828 "The Insulated Gate Transistor: A New Three-Terminal MOS-Controlled Bipolar Power Device" by B. J. Baliga et al., for example. FIG. 1 is a sectional view showing a structure of a conventional n-channel IGBT cell, and FIG. 2 is a circuit diagram showing an equivalent circuit thereof.
Referring to FIG. 1, numeral 1 indicates a P.sup.+ -type collector layer consisting of a P.sup.+ -type semiconductor substrate, which is provided on one major surface thereof with an N.sup.- -type epitaxial layer 2. A P-type well region 3 is partially formed in the surface of the N.sup.- -type epitaxial layer 2 by selectively diffusing a P-type impurity, and an N.sup.+ -type emitter region 4 is formed partially in the surface of the P-type well region 3 by selectively diffusing an N-type impurity of high concentration. A gate insulation film 5 is formed on the surface of the P-type well region 3 between the surfaces of the N.sup.- -type epitaxial layer 2 and the N.sup.+ -type emitter region 4. This gate insulation film 5 also covers the surface of the N.sup.- -type epitaxial layer 2 to be integrated with a gate insulation film of an adjacent IGBT cell. A gate electrode 6 of polysilicon, for example, is formed on the gate insulation film 5, and an emitter electrode 7 of metal such as aluminum is formed to be electrically connected to both of the P-type well region 3 and the N.sup.+ -type emitter region 4. The gate electrode 6 and the emitter electrode 7 are provided in multilayer structure through an insulation film 8, to be commonly electrically connected to each cell forming the IGBT device. A collector metal electrode 9 is formed on the back surface of the P.sup.+ -type collector layer 1 in common with each of the IGBT cells.
N-channel MOS structure is provided in the vicinity of the surface of the P-type well region 3 between the N.sup.- -type epitaxial layer 2 and the N.sup.+ -type emitter region 4. A positive voltage is applied to the gate electrode 6 through a gate terminal G so that electrons flow from the N.sup.+ -type emitter region 4 to the N.sup.- -type epitaxial layer 2 through a channel formed in the vicinity of the surface of the P-type well region 3 under the gate electrode 6. Symbol I.sub.e indicates electron current thus carried. On the other hand, positive holes, which are minority carriers, are injected from the P.sup.+ -type collector layer 1 into the N.sup.- -type epitaxial layer 2. A portion of the holes dissipate through recombination with the aforementioned electrons, while the remaining holes flow in the P-type well region 3 as hole current I.sub.h. Thus, the IGBT basically operates in a bipolar manner and conductivity is increased in the N.sup.- -type epitaxial layer 2 due to a conductivity modulation effect, whereby lower ON-state voltage and larger current capacity can be implemented in contrast to a conventional power MOS.
It is to be noted that a parasitic PNPN thyristor structure is present in the IGBT cell, as is obvious from an equivalent circuit shown in FIG. 2. Such a parasitic thyristor is formed by an NPN transistor 10 defined by the N.sup.- -type epitaxial layer 2, the P-type well region 3 and the N.sup.+ -type emitter region 4 and a PNP transistor 11 defined by the P.sup.+ -type collector layer 1, the N.sup.- -type epitaxial layer 2 and the P-type well region 3. When both of the transistors 10 and 11 enter their respective operating states and when the sum of current gains .alpha..sub.1 and .alpha..sub.2 thereof becomes 1, the parasitic thyristor conducts and thereby causes a latch-up phenomenon. Since the thickness of the N.sup.- -type epitaxial layer 2 serving as the base of the PNP transistor 11 is much larger than the carrier diffusion length, the value .alpha..sub.2 is relatively small. Further, there is a short circuit between the emitter and the base of the NPN transistor 10, so that the transistor barely enters the ON state. Therefore, no latch-up phenomenon is caused in the normal operating state, and the IGBT cell operates as a composite element of an n-channel MOSFET 12 and the PNP transistor 11. In this case, the base current of the PNP transistor 11 is controlled by the n-channel MOSFET 12 and, therefore, main current I.sub.C flowing from a collector terminal C of the IGBT can be controlled by a control signal applied to the gate terminal G. Assuming that I.sub.E represents current flowing in an emitter terminal E, the main current I.sub.C is EQU I.sub.C =I.sub.E =I.sub.e +I.sub.h ( 1)
When the main current I.sub.C of the IGBT is increased by some external cause such as noise applied to the gate terminal G, the electron current I.sub.e and the hole current I.sub.h are increased. If the hole current I.sub.h exceeds a certain value, the NPN transistor 10 conducts by a voltage drop caused by resistance R.sub.B of the P-type well region 3, and .alpha..sub.1 +.alpha..sub.2 =1 is satisfied because of increase of the current gain .alpha..sub.2 of the NPN transistor 10, so that the parasitic thyristor conducts. Thus, the IGBT enters a latch-up state. The main current I.sub.C of the IGBT cannot be controlled by the control signal applied to the gate terminal G in this state, and hence an excessive unlimited main current I.sub.C flows. In order to prevent such a latch-up phenomenon, impurity concentration of the P-type well region 3 must be increased to reduce the resistance, and the ratio of the hole current I.sub.h, flowing under the N.sup.+ -type emitter region 4 toward the emitter electrode 7, must be reduced.
FIG. 3 is a sectional view showing an example of IGBT cell structure generally employed for preventing the latch-up phenomenon. Such a structure is shown in IEDM 83, PP. 79-82, "Improved COMFETs with Fast Switching Speed and High-Current Capability" by A. M. Goodman et al., for example. Referring to FIG. 3, a P-type well region 3 of each IGBT cell, which is square when presented in a plan view, is provided in its central portion with a P.sup.+ -type region 13 which is formed by diffusing a high concentrate of P-type impurity of the same conductivity type as the region 3. Thus, resistance of the P-type well region 3 is reduced and hole current I.sub.h flowing in the central portion of the P-type well region 3 is relatively increased in ratio as compared with hole current I.sub.h flowing under an N.sup.+ -type emitter region 4, so that an NPN transistor 10 is prevented from transision into a conducting state.
FIG. 4 is a diagrammatical perspective sectional view illustrating another example of IGBT cell structure generally employed for preventing the latch-up phenomenon. Such a structure is shown in IEDM 85, PP. 150-153 "Experimental and Numerical Study of Non-Latch-Up Bipolar-Mode MOSFET Characteristics" by A. Nakagawa et al., for example. Referring to FIG. 4, a P-type well region 3 is formed in a strip pattern and an N.sup.+ -type emitter region 4 is formed in a partially removed pattern. Thus, parts of the P-type well region 3, from which the N.sup.+ -type emitter region 4 is removed, are adapted to serve as bypasses for hole current I.sub.h, so that the ratio of the hole current I.sub.h flowing under the N.sup.+ -type emitter region 4 is reduced. Further, a P.sup.+ -type region 13, which is similar to that shown in FIG. 3, is provided.
In order to employ the structure shown in FIG. 3, the P-type well region 3 must be deeply formed particularly in an IGBT device of high breakdown voltage, and hence the P.sup.+ -type region 13 of high impurity concentration must also be formed to a deep position. Since the P.sup.+ -type region 13 is formed by diffusion from the surface, concentration distribution of the impurity is inevitably lowered as the depth is increased. Therefore, resistance R.sub.B1 in vertical direction of the P-type well region 3 cannot be sufficiently lowered in a deep portion. Further, although the P.sup.+ -type region 13 is preferably formed over the entire region under the N.sup.+ -type emitter region 4, the same must not reach a channel region under the gate electrode 6, in order to avoid changing the threshold voltage of the MOSFET 12. Therefore, the P.sup.+ -type region 13 must be considerably separated from the channel region in view of various errors in formation, and hence the resistance R.sub.B2, in a direction transverse to the P-type well region 3, cannot be sufficiently lowered in a portion close to the channel. Thus, the structure shown in FIG. 3 is insufficient to cope with the latch-up phenomenon.
In the structure shown in FIG. 4, on the other hand, channels are inevitably decreased because of partial removal of the N.sup.+ -type emitter region 4. Such decrease of channels is disadvantageous for large current capacity. Further, since a top plan pattern of the IGBT cell shows an elongated rectangle, it is difficult to implement an IGBT device of high current capacity having a number of parallel-connected IGBT cells with a higher density cell arrangement when compared to those having square IGBT cells.